The present invention relates to a circuit for protecting a semiconductor device from an electrostatic discharge, and more particularly to an electrostatic discharge protective circuit having a low operating voltage.
A typical semiconductor device includes an electrostatic discharge protective circuit for protecting an internal circuit from electrostaticity which flows from the input/output pad to the internal circuit.
The electrostatic discharge protective circuit prevents the electrostaticity from being discharged into the internal circuit when a pin of the integrated circuit contacts an electrified human-body or machine.
Meanwhile, semiconductor devices are being manufactured to achieve higher speeds and are becoming highly integrated; and thus the gate of the semiconductor device gradually thins. Therefore, defects in the semiconductor device occur when convention electrostatic discharge protective circuits allow electrostaticity to flow into the internal circuit.
This can be observed in a conventional electrostatic discharge protective circuit such as the electrostatic discharge protective circuit illustrated in FIG. 1. In the conventional electrostatic discharge protective circuit, the internal circuit and the gate oxide film of the electrostatic discharge protective device may be destroyed before the electrostaticity is discharged due to the high voltage.
Referring to FIG. 1, when positive electrostaticity flows through a pad and is discharged to a VSS pad, a GGNMOS N10 performs a parasitic bipolar operation and a GPPMOS p10 performs a parasitic diode operation to apply the positive electrostaticity to a power supply line VCC, and the electrostacity is discharged to a ground line VSS through a GGNMOS N14.
When negative electrostatic flows through the pad and is discharged to a VCC pad, the GPPMOS P10 performs the parasitic bipolar operation and the negative electrostaticity is then discharged to the power supply line VCC through both the GGNMOS N14, which performs a parasitic bipolar operation, and the GGNMOS N10, which performs a parasitic diode operation.
Additionally, a CDM transistor with a resistor R10 and a GGNMOS N12 is provided between input buffers 106 to protect the internal circuit.
Another conventional electrostatic discharge protective circuit is illustrated in FIG. 2. The conventional electrostatic discharge protective circuit of FIG. 2 discharges the positive electrostaticity flowing from the input/output pad to the VSS pad. At this time, a GPPMOS P20 acting as a parasitic diode discharges the positive electrostaticity to the power supply line. The positive electrostaticity flows from the input/output pad to the power supply line, and when the voltage dropped by the capacitor C20 and the resistor 22 is higher than the threshold voltage of a GCNMOS N24, the GCNMOS N24 turns on to discharge the positive electrostaticity to the ground pad V33. At this time, the operating voltage of GCNMOS N24 is about 6.2V.
Subsequently, the GGNMOS N20 is turned on to discharge the positive electrostaticity flowing into the input/output pad to the ground pad VSS through the ground line. At this time, the operating voltage of GGNMOS N20 is about 8.3V.
However, if electrostaticity having a high voltage continues to flow before discharge to the GCNMOS N24 is completed, a problem occurs, in that the gate oxide of the internal circuit can be destroyed before the GGNMOS N20 is operated.
On the other hand, in the case where negative electrostaticity flows in and is discharged to the VCC pad, the GPPMOS P20 performs the parasitic bipolar operation at about 8.1V, and thus the gate oxide of the internal circuit can be destroyed before the GPPMOS P20 is operated, as described above.
As mentioned above, since the conventional electrostatic discharge protective devices have a high operating voltage, the gate oxide films of the internal circuit, which have a low gate breakdown voltage, and the electrostatic discharge protective device can be destroyed when the conventional electrostatic discharge protective devices are utilized.